1. Field of the Invention
The present invention relates to a semiconductor device including a resistance element as its component, and particularly to circuitry in which erroneous operation due to noise in the resistance element region can be prevented as well as to its layout. More particularly, the present invention relates to a structure for improving noise immunity of an internal power supply voltage generating circuit in a semiconductor memory device.
2. Description of the Background Art
In a semiconductor device, resistance elements are employed in various portions for regulation and/or generation of voltage and current. As an example of circuitry utilizing resistance elements, consideration is made on a voltage down converter in a dynamic random access memory (DRAM). This internal voltage down converter down-converts an external supply voltage internally to produce an internal supply voltage lower than the external supply voltage. By utilizing the supply voltage which has been internally down-converted, compatibility with memories of earlier generations is maintained while commaring breakdown voltage characteristics of the elements which have been miniaturized as storage capacity has been made larger.
FIG. 13 schematically shows an entire structure of a conventional dynamic random access memory. Referring to FIG. 13, a dynamic random access memory 1 includes an internal voltage down converter 3 for receiving and down-converting an external supply voltage extVcc applied externally to terminal 2 so as to produce an internal supply voltage intVcc, a control circuit 4 operating with internal supply voltage intVcc from internal voltage down converter 3 as its one operational supply voltage to perform controls required for selection of a memory cell and writing/reading of data in accordance with externally applied signals, and a memory array 5 including a plurality of dynamic type memory cells arranged in a matrix.
Control circuit 4 receives a row address strobe signal /RAS for instructing the start of memory cell row selecting operation, a column address strobe signal /CAS for instructing the start of memory cell column selecting operation of memory array 5, a write enable signal /WE for designating data writing operation, an output enable signal /OE for instructing data output, and an address signal An.
Memory array 5 also includes various peripheral circuits such as a sense amplifier provided corresponding to each of the memory columns for sensing and amplifying memory cell data on a corresponding column, a decoder for decoding address signals applied from control circuit 4 to select a memory cell row and a memory cell column of memory array 5, a column selecting gate for connecting the selected column to internal data bus (not shown explicitly), and an equalizing/precharging circuit for precharging and equalizing each of the memory cell columns at a prescribed potential. These peripheral circuits of the memory array are also operated with internal supply voltage intVcc from internal voltage down converter 3 as one operational supply voltage.
Dynamic random access memory 1 further includes an input circuit 6 operating with internal supply voltage intVcc from internal voltage down converter 3 as its one operational supply voltage for producing internal write data from external write data DQn applied to data input/output terminal 7 under the control of control circuit 4 for writing into a selected memory cell of memory array 5, and an output circuit 8 operating with internal supply voltage intVcc as one operational supply voltage for converting the data of selected memory cell of memory array 5 into external read out data at the level of external supply voltage extVcc under the control of control circuit 4 and outputting it to data input/output terminal 7.
In this dynamic random access memory 1, when row address strobe signal /RAS is changed to an active state of L level, with address signal An applied currently used as the row address a row selecting operation at memory array 5 is performed and data of the memory cells connected to the selected row are sensed, amplified and latched by sense amplifiers. Then, when column address strobe signal /CAS is driven to L level of active state, column selecting operation is started in memory array 5 according to address signal An applied currently. When write enable signal /WE is at L level in an active state, input circuit 6 is activated, internal write data is produced from data DQn applied to data input/output terminal 7 to be written into the memory cell arranged corresponding to intersection of the selected row and the selected column of memory array 5. Upon activation of output enable signal /OE, output circuit 8 is activated and data of the selected memory cell of memory array 5 is converted to the level of external supply voltage extVcc to be output to data input/output terminal 7.
Internal voltage down converter 3 includes a reference voltage generating circuit 10 for generating a constant reference voltage Vref having no dependency on external supply voltage extVcc from external supply voltage extVcc when this external supply voltage extVcc is at a prescribed voltage level, and an internal voltage generating circuit 12 for producing internal supply voltage intVcc from external supply voltage extVcc in accordance with reference voltage Vref generated from this reference voltage generating circuit 10. Internal voltage generating circuit 12 produces internal supply voltage intVcc having a level substantially equal to the level of this reference voltage Vref on internal power supply line 13.
FIG. 14 shows an example of a specific structure of reference voltage generating circuit 10 and internal voltage generating circuit 12 in internal voltage down converter 3 of FIG. 13. Referring to FIG. 14, reference voltage generating circuit 10 includes a constant current generating circuit 10a coupled between power supply node 2a supplied with external supply voltage extVcc and a ground node for generating a constant current i0 having no dependency on this external supply voltage extVcc, and a constant voltage generating circuit 10b connected between power supply node 2a and the ground node for converting constant current i0 from constant current generating circuit 10a into voltage to generate a constant reference voltage Vref having no dependency on external supply voltage extVcc.
Internal voltage generating circuit 12 compares this reference voltage Vref with internal supply voltage intVcc on internal power supply line 13, supplies current from power supply node 2a to internal power supply line 13 according to the result of comparison, holds internal supply voltage intVcc at the level of reference voltage Vref.
Constant current generating circuit 10a includes a resistance element R0 of high resistance connected between power supply node 2a and node N1; a p channel MOS transistor Q1 having one conduction node (source) connected to power supply node 2a, the other conduction node (drain) connected to node N2 and a control gate connected to node N1; a p channel MOS transistor Q2 having one conduction node connected to node N1, the other conduction node connected to node N3 and a control gate connected to node N2; an n channel MOS transistor Q3 having one conduction node (drain) connected to node N2, the other conduction node connected to the ground node and a control gate connected to power supply node 2a; and an n channel MOS transistor Q4 having its one conduction node and control gate connected to node N3 and the other conduction node connected to the ground node.
The channel length of L of MOS transistor Q3 is made sufficiently longer than that of MOS transistor Q1, and current driving capability of MOS transistor Q3 is made sufficiently smaller than that of MOS transistor Q1. Resistance element R0 has a large resistance value such as several hundred K.OMEGA. to 1M.OMEGA.. Operation of this constant current generating circuit will now be described in the following.
When power supply voltage extVcc is applied externally and its voltage level is made higher to cause current to flow through resistance element R0, voltage drop occurs across this resistance element R0. Node N1 is connected to the control gate of p channel MOS transistor Q1. Accordingly, when the voltage drop across this resistance element R0 exceeds the absolute value of threshold voltage of MOS transistor Q1, this MOS transistor Q1 is rendered conductive, so that current flows from power supply node 2a through MOS transistors Q1 and Q3.
As described above, MOS transistor Q3 has its channel length L sufficiently long and its current driving capability sufficiently smaller than that of MOS transistor Q1. Meanwhile, node N2 is connected to the control gate of p channel MOS transistor Q2 which also supplies current from resistance element R0 to MOS transistor Q4 according to the potential at node N2. Resistance element R0 is a resistor formed of, for example, polycrystalline silicon layer and has a high resistance value. The current flowing to MOS transistors Q2 and Q4 is sufficiently small.
When the potential at node N1 is made higher, the conductance of MOS transistor Q1 is reduced, which leads to reduction in amount of current flowing to node N2. Then, the potential at node N2 is lowered, and the conductance of MOS transistor Q2 is made higher, so that large amount of current is caused to flow and the potential at node N1 is made lower. On the contrary, when the potential at node N1 is made lower, the conductance of MOS transistor Q1 is made higher so that the potential at node N2 is increased and the amount of current flowing through MOS transistor Q2 is reduced. Owing to this feedback operation of MOS transistors Q1 and Q2, the current flowing to MOS transistors Q1 and Q2 is made constant. Since the current driving capability of MOS transistor Q3 is sufficiently small, the voltage between the gate and the source of this MOS transistor Q1 is established at Vth(p). Here, Vth(p) represents the absolute value of the threshold voltage of each of MOS transistors Q1 and Q2. That is, a potential of node N1 would be extVcc-Vth(p). Accordingly, current i0 flowing through resistance element R1 would be expressed as: EQU i0=Vth(p)/R0
where the resistance value of resistance element R0 is indicated by an identical reference character R0. This resistance value R0 is, as has been mentioned before, as high as several hundred K.OMEGA. to 1M.OMEGA.. Also, current i0 is of a sufficiently low value. Source-gate voltage of MOS transistor Q2 would be Vth(p). Thus, potential V(N2) of node N2 would be represented in the following expression: EQU V(N2)=V(N1)-Vth(p)=extVcc-2.multidot.Vth(p)
where V(N1) indicates the voltage of node N1. Accordingly, source-drain voltage of p channel MOS transistor Q1 is a constant voltage 2.multidot.Vth(p) having no dependency on external supply voltage extVcc. Similarly, the gate-source voltages of MOS transistors Q1 and Q2 would also be constant voltage (Vth(p)) having no dependency on external power supply voltage extVcc. Accordingly, the difference between the voltage of node N1 and external supply voltage extVcc of power supply node 2a would also be of a constant value of Vth(p). Current i0=Vth(p)/R0 flowing through this resistance element R0 and MOS transistors Q2 and Q4 would also be constant. Thus, constant current having no dependency on external supply voltage extVcc is obtained.
Constant voltage generating circuit 10b includes an n channel MOS transistor Q5 connected between node N4 and a ground node and having its gate connected to node N3, a p channel MOS transistor Q6 connected between power supply node 2a and node N4 and having its control gate connected to node N4, a p channel MOS transistor Q7 connected between power supply node 2a and node N5 and having its gate connected to node N4, and a resistance element R1 connected between node N5 and the ground node. Reference voltage Vref is output from node N5. Operation of this constant voltage generating circuit 10b will now be described in the following.
MOS transistors Q4 and Q5 form a current mirror circuit. If they have the same size (i.e., ratio of channel length to channel width), the current flowing to MOS transistor Q5 would be of the same magnitude as the current i0 flowing through MOS transistor Q4. MOS transistors Q6 and Q7 form a current mirror circuit. If they have the same size, the current flowing through these MOS transistors Q6 and Q7 would be of same magnitude. Current i0 flows to MOS transistor Q5, and then through MOS transistor Q6, and accordingly, to MOS transistor Q7. Assuming that the resistance value of resistance element R1 is expressed as R1, voltage generated at node n5 is i0.multidot.R1. Therefore, reference voltage Vref output from this node N5 is represented by the following expression. EQU Vref=i0.multidot.R1=Vth(p).multidot.R1/R0
As is clearly understood from the above expression, this reference voltage Vref is determined by the resistance value of resistance elements R0 and R1 as well as threshold voltages of MOS transistors Q1 and Q2, and is at a constant voltage level having no dependency on external supply voltage extVcc. The internal voltage generating circuit generates internal supply voltage intVcc according to this reference voltage Vref.
Internal voltage generating circuit 12 includes an n channel MOS transistor Q8 connected between node N6 and node N8 and receiving reference voltage Vref at its gate, an n channel MOS transistor Q9 connected between node N7 and node N8 and having its gate connected to internal power supply line 13, a p channel MOS transistor Q10 connected between power supply node 2a and node N6 and having its gate connected to node N7, a p channel MOS transistor Q11 connected between power supply node 2a and node N7 and having its gate connected to node N7, an n channel MOS transistor Q12 connected between node N8 and the ground node and receiving an activation signal .phi. at its gate, and a p channel MOS transistor Q13 connected between power supply node 2a and internal power supply line 13 and having its gate connected to node N6. Activation signal .phi. is activated when the dynamic random access memory is in an active state, that is, when the memory cell selecting operation is being performed. Operation of this internal voltage generating circuit 12 will now be described in the following.
MOS transistors Q8 and Q9 form a differential comparison stage. When internal supply voltage intVcc on internal power supply line 13 is higher than reference voltage Vref, MOS transistor Q9 would have a conductance higher than that of MOS transistor Q8 and the current flowing through it would be larger than the current flowing through MOS transistor Q8. Current is supplied to this MOS transistor Q9 via MOS transistor Q11. MOS transistors Q11 and Q10 form a current mirror circuit in which the current flowing through MOS transistor Q10 is of the same magnitude as the current flowing through MOS transistor Q11. Accordingly, in this state, MOS transistor Q8 cannot discharge all of the current supplied via MOS transistor Q10, the potential of node N6 is made higher, the gate potential of MOS transistor Q13 is made higher, and MOS transistor Q13 would supply smaller amount of current or would supply no current.
On the contrary, when internal supply voltage intVcc is lower than reference voltage Vref, the conductance of MOS transistor Q8 would be larger than the conductance to MOS transistor Q9. In this case, conversely, MOS transistor Q8 will discharge all of the current supplied via MOS transistor Q10 to lower the potential of node N6, and thus MOS transistor Q13 would have a larger conductance and would supply current from power supply node 2a to internal power supply line 13 so as to raise internal supply voltage intVcc on internal power supply line 13. Therefore, upon operation of internal voltage generating circuit 12, the level of internal supply voltage intVcc is maintained at the level of reference voltage Vref.
During standby, activation signal .phi. is at L level in an inactive state, and MOS transistor Q12 is turned off. This internal voltage generating circuit 12 is inactivated, changes the voltage level of node N6 to the level of external supply voltage extVcc, and turns off MOS transistor Q13.
FIG. 15A schematically shows a two-dimensional layout of resistance element R0 included in constant current circuit 10a. As is shown in FIG. 15, resistance element R0 includes a plurality of first resistance portions Ra extending in the vertical direction in the drawing, and second resistance portions Rb for alternately connecting one-side ends of the adjacent first resistance portions Ra. The opposite ends of resistance element R0 are electrically connected to power supply node and node N1 respectively via contact holes Na and Nb. Resistance element R0 is formed of polycrystalline silicon. In this resistor using polycrystalline silicon, its sheet resistance is relatively low. Accordingly, in order to form a large resistance value ranging from several hundreds of K.OMEGA. to several M.OMEGA. required in the constant current circuit within a limited small area, the plurality of first resistance portions Ra having small line width are arranged in parallel and are electrically connected in an alternating manner to form a zigzag shape so that the entire length of this resistance element R0 would be equivalently increased so as to implement a high resistance value.
FIG. 15B is a schematic diagram of a cross sectional structure taken along line 15A--15A of FIG. 15A. Normally, such resistance element R0 is formed on a semiconductor substrate P-SUB with a field insulating film FD having a large thickness therebetween, in order to reduce the parasitic capacitance between the element and the substrate. Semiconductor substrate P-SUB is a P type semiconductor layer which is normally fixed at the level of bias voltage VBB of negative potential.
In this structure shown in FIG. 15B, parasitic capacitance Cp is formed between each of first resistance portions Ra and semiconductor substrate P-SUB. Although not shown in FIG. 15B, second resistance portion Rb has a parasitic capacitance to semiconductor substrate P-SUB. When the resistance value of this resistance element R0 is high and its entire length is made longer, the value of combined parasitic capacitance Cpara of this parasitic capacitance Cp is increased to an unnegligible value. The following is a description on the influence of this parasitic capacitance Cpara to the operation of the circuitry.
FIG. 16A shows how parasitic capacitance Cpara is connected in constant current generating circuit 10a. Although parasitic capacitance Cpara is arranged dispersedly over resistance element R0, it is shown equivalently as one combined parasitic capacitance Cpara in FIG. 16A.
Now, the operation of constant current generating circuit 10a shown in FIG. 16A during the rise in external supply voltage extVcc is described with reference to the waveforms shown in FIG. 16B.
Until time t0, external supply voltage extVcc is stabilized at the level of voltage V1. Under this state, the potential of node N1 is V1-Vth(p) as has been already described. Accordingly, current i0 flowing through resistance element R0 is expressed as follows. EQU i0=(extVcc-V(N1))/R0=Vth(p)/R0
Reference voltage Vref produced by constant current i0 is also maintained at a prescribed voltage level.
At time t0, external supply voltage extVcc starts rising and attains the level of voltage V2 at time t1. When parasitic capacitance Cpara is not present, the potential of node N1 is increased in accordance with the rise of this external supply voltage extVcc with a constant difference (Vth(p)) as shown by a solid line in FIG. 16B. However, since parasitic capacitance Cpara is present with respect to resistance element R0, increase in potential at node N1 is moderate in accordance with time constant determined by resistance element R0 and the capacitance value of parasitic capacitor Cpara, as shown by broken line in FIG. 16B.
During the period between time t0 to time t1, voltage across resistance element R0 between power supply node 2a and node N1 is made higher than voltage Vth(p). Therefore, in this state, current i0 is increased (since extVcc-V(N1)&gt;Vth(p)), and accordingly, the level of reference voltage Vref is also made higher. Reference voltage Vref is made higher in accordance with this rise of external supply voltage extVcc, and the level of internal supply voltage intVcc is also raised correspondingly.
A transistor of miniaturized internal circuitry is operated according to this internal supply voltage intVcc, and therefore, a problem arises in which the breakdown voltage characteristics of the components of the internal circuitry is degraded. In addition, since the signal amplitude of this internal circuitry changes corresponding to the increased internal power supply voltage, there would be a problem that power dissipation is increased. Moreover, the MOS transistor (insulating gate type field effect transistor) which is a component of the internal circuitry would have its gate potential increased according to increase in this internal power supply voltage intVcc (since the voltage level of the internal signal is made higher) so that operation speed is also changed, changing the timing of defining of the internal signals and leading to a possibility of erroneous operation in the internal circuitry.
When external power supply voltage extVcc is made constant at the level of voltage V2 at time t1, the difference between this external power supply voltage extVcc and the voltage at node N1 is gradually reduced, the current value of constant current i0 is also gradually reduced to finally attain a desired current value (Vth(p))/R0, and accordingly, reference voltage Vref is also recovered to a prescribed voltage level.
Similarly, when the level of external power supply voltage extVcc is lowered, reduction rate in the voltage at node N1 is made moderate. The voltage across resistance element R0 is reduced to be lower than a prescribed voltage level Vth(p), and according to this reduction, the value of constant current i0 is reduced to be lower than a predetermined value. According to this reduction, reference voltage Vref is also lowered, and internal power supply voltage intVcc is also lowered. Accordingly, in this state, there occurs a possibility that the internal circuitry may perform an erroneous operation due to a bump of internal power supply voltage.
When polycrystalline silicon resistor is employed for resistance element R0 as described above, its large parasitic capacitance degrades the response characteristics for variation of external supply voltage extVcc of constant current generating circuit and the internal supply voltage may be varied through this variation in the constant current.
This problem of response characteristics being degraded by the parasitic capacitance accompanying the resistance element occurs not only with the resistance element connected to a source of the constant voltage such as external power supply voltage as described above, but also with a resistance element generally provided in a signal propagating path. In this case, the signal cannot be conducted with high speed, and fast operation is inhibited.
In addition, a low pass filter formed of resistance element and a capacitor is generally used in order to prevent such influence of the noise, but when such a low pass filter is employed, the capacitor requires a relatively large layout area, although it is desirable to reduce the area occupied by this capacitor as much as possible from the aspect of integration.